1. Field of the Invention
The invention relates to memories, and more particularly to arrays of MNOS memory circuits utilizing a varactor bootstrap circuit to boost the row select signals during erase and write operations.
2. Description of the Prior Art
Typical prior art solid state MNOS memory arrays require that the select voltage coupled to the gate of the transistors comprising the array have a higher value during the clear and erase operations than during the interrogate operations. In prior art MNOS memory arrays this has resulted in the output transistors of the address decoders having a relatively high voltage drop between the drain and source. This increased the power consumption because of the high voltage drop across these transistors and reduced the amplitude of the select signals. The net result was high power consumption and impaired memory operation.